# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s

---
name:            v8s8_smin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: v8s8_smin
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<8 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %smin:_(<8 x s8>) = G_SMIN %vec, %vec1
    ; CHECK-NEXT: $x0 = COPY %smin(<8 x s8>)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %vec:_(<8 x s8>) = G_IMPLICIT_DEF
    %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
    %smin:_(<8 x s8>) = G_SMIN %vec, %vec1
    $x0 = COPY %smin
    RET_ReallyLR implicit $x0

...
---
name:            v16s8_smin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v16s8_smin
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<16 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %smin:_(<16 x s8>) = G_SMIN %vec, %vec1
    ; CHECK-NEXT: $q0 = COPY %smin(<16 x s8>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<16 x s8>) = G_IMPLICIT_DEF
    %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
    %smin:_(<16 x s8>) = G_SMIN %vec, %vec1
    $q0 = COPY %smin
    RET_ReallyLR implicit $q0

...
---
name:            v32s8_smin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v32s8_smin
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
    ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(<16 x s8>) = G_SMIN [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<16 x s8>) = G_SMIN [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[SMIN]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK-NEXT: G_STORE [[SMIN1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
    %vec:_(<32 x s8>) = G_IMPLICIT_DEF
    %vec1:_(<32 x s8>) = G_IMPLICIT_DEF
    %smin:_(<32 x s8>) = G_SMIN %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %smin(<32 x s8>), %1(p0) :: (store (<32 x s8>))

...
---
name:            v4s16_smin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: v4s16_smin
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %smin:_(<4 x s16>) = G_SMIN %vec, %vec1
    ; CHECK-NEXT: $x0 = COPY %smin(<4 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %vec:_(<4 x s16>) = G_IMPLICIT_DEF
    %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
    %smin:_(<4 x s16>) = G_SMIN %vec, %vec1
    $x0 = COPY %smin
    RET_ReallyLR implicit $x0

...
---
name:            v8s16_smin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v8s16_smin
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<8 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %smin:_(<8 x s16>) = G_SMIN %vec, %vec1
    ; CHECK-NEXT: $q0 = COPY %smin(<8 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<8 x s16>) = G_IMPLICIT_DEF
    %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
    %smin:_(<8 x s16>) = G_SMIN %vec, %vec1
    $q0 = COPY %smin
    RET_ReallyLR implicit $q0

...
---
name:            v16s16_smin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v16s16_smin
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
    ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(<8 x s16>) = G_SMIN [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<8 x s16>) = G_SMIN [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[SMIN]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK-NEXT: G_STORE [[SMIN1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
    %vec:_(<16 x s16>) = G_IMPLICIT_DEF
    %vec1:_(<16 x s16>) = G_IMPLICIT_DEF
    %smin:_(<16 x s16>) = G_SMIN %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %smin(<16 x s16>), %1(p0) :: (store (<16 x s16>))

...
---
name:            v2s32_smin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: v2s32_smin
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %smin:_(<2 x s32>) = G_SMIN %vec, %vec1
    ; CHECK-NEXT: $x0 = COPY %smin(<2 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %vec:_(<2 x s32>) = G_IMPLICIT_DEF
    %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
    %smin:_(<2 x s32>) = G_SMIN %vec, %vec1
    $x0 = COPY %smin
    RET_ReallyLR implicit $x0

...
---
name:            v4s32_smin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v4s32_smin
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<4 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %smin:_(<4 x s32>) = G_SMIN %vec, %vec1
    ; CHECK-NEXT: $q0 = COPY %smin(<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<4 x s32>) = G_IMPLICIT_DEF
    %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
    %smin:_(<4 x s32>) = G_SMIN %vec, %vec1
    $q0 = COPY %smin
    RET_ReallyLR implicit $q0

...
---
name:            v8s32_smin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v8s32_smin
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
    ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(<4 x s32>) = G_SMIN [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<4 x s32>) = G_SMIN [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[SMIN]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK-NEXT: G_STORE [[SMIN1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
    %vec:_(<8 x s32>) = G_IMPLICIT_DEF
    %vec1:_(<8 x s32>) = G_IMPLICIT_DEF
    %smin:_(<8 x s32>) = G_SMIN %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %smin(<8 x s32>), %1(p0) :: (store (<8 x s32>))

...
---
name:            v2s64_smin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v2s64_smin
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), %vec(<2 x s64>), %vec1
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[SEXT_INREG]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
    ; CHECK-NEXT: %smin:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
    ; CHECK-NEXT: $q0 = COPY %smin(<2 x s64>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<2 x s64>) = G_IMPLICIT_DEF
    %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
    %smin:_(<2 x s64>) = G_SMIN %vec, %vec1
    $q0 = COPY %smin
    RET_ReallyLR implicit $q0

...
---
name:            v4s64_smin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v4s64_smin
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
    ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
    ; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
    %vec:_(<4 x s64>) = G_IMPLICIT_DEF
    %vec1:_(<4 x s64>) = G_IMPLICIT_DEF
    %smin:_(<4 x s64>) = G_SMIN %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %smin(<4 x s64>), %1(p0) :: (store (<4 x s64>))

...
---
name:            v8s8_umin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: v8s8_umin
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<8 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %umin:_(<8 x s8>) = G_UMIN %vec, %vec1
    ; CHECK-NEXT: $x0 = COPY %umin(<8 x s8>)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %vec:_(<8 x s8>) = G_IMPLICIT_DEF
    %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
    %umin:_(<8 x s8>) = G_UMIN %vec, %vec1
    $x0 = COPY %umin
    RET_ReallyLR implicit $x0

...
---
name:            v16s8_umin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v16s8_umin
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<16 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %umin:_(<16 x s8>) = G_UMIN %vec, %vec1
    ; CHECK-NEXT: $q0 = COPY %umin(<16 x s8>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<16 x s8>) = G_IMPLICIT_DEF
    %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
    %umin:_(<16 x s8>) = G_UMIN %vec, %vec1
    $q0 = COPY %umin
    RET_ReallyLR implicit $q0

...
---
name:            v32s8_umin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v32s8_umin
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
    ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(<16 x s8>) = G_UMIN [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<16 x s8>) = G_UMIN [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[UMIN]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK-NEXT: G_STORE [[UMIN1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
    %vec:_(<32 x s8>) = G_IMPLICIT_DEF
    %vec1:_(<32 x s8>) = G_IMPLICIT_DEF
    %umin:_(<32 x s8>) = G_UMIN %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %umin(<32 x s8>), %1(p0) :: (store (<32 x s8>))

...
---
name:            v4s16_umin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: v4s16_umin
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %umin:_(<4 x s16>) = G_UMIN %vec, %vec1
    ; CHECK-NEXT: $x0 = COPY %umin(<4 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %vec:_(<4 x s16>) = G_IMPLICIT_DEF
    %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
    %umin:_(<4 x s16>) = G_UMIN %vec, %vec1
    $x0 = COPY %umin
    RET_ReallyLR implicit $x0

...
---
name:            v8s16_umin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v8s16_umin
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<8 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %umin:_(<8 x s16>) = G_UMIN %vec, %vec1
    ; CHECK-NEXT: $q0 = COPY %umin(<8 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<8 x s16>) = G_IMPLICIT_DEF
    %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
    %umin:_(<8 x s16>) = G_UMIN %vec, %vec1
    $q0 = COPY %umin
    RET_ReallyLR implicit $q0

...
---
name:            v16s16_umin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v16s16_umin
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
    ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(<8 x s16>) = G_UMIN [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<8 x s16>) = G_UMIN [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[UMIN]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK-NEXT: G_STORE [[UMIN1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
    %vec:_(<16 x s16>) = G_IMPLICIT_DEF
    %vec1:_(<16 x s16>) = G_IMPLICIT_DEF
    %umin:_(<16 x s16>) = G_UMIN %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %umin(<16 x s16>), %1(p0) :: (store (<16 x s16>))

...
---
name:            v2s32_umin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: v2s32_umin
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %umin:_(<2 x s32>) = G_UMIN %vec, %vec1
    ; CHECK-NEXT: $x0 = COPY %umin(<2 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %vec:_(<2 x s32>) = G_IMPLICIT_DEF
    %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
    %umin:_(<2 x s32>) = G_UMIN %vec, %vec1
    $x0 = COPY %umin
    RET_ReallyLR implicit $x0

...
---
name:            v4s32_umin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v4s32_umin
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<4 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %umin:_(<4 x s32>) = G_UMIN %vec, %vec1
    ; CHECK-NEXT: $q0 = COPY %umin(<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<4 x s32>) = G_IMPLICIT_DEF
    %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
    %umin:_(<4 x s32>) = G_UMIN %vec, %vec1
    $q0 = COPY %umin
    RET_ReallyLR implicit $q0

...
---
name:            v8s32_umin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v8s32_umin
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
    ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(<4 x s32>) = G_UMIN [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<4 x s32>) = G_UMIN [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[UMIN]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK-NEXT: G_STORE [[UMIN1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
    %vec:_(<8 x s32>) = G_IMPLICIT_DEF
    %vec1:_(<8 x s32>) = G_IMPLICIT_DEF
    %umin:_(<8 x s32>) = G_UMIN %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %umin(<8 x s32>), %1(p0) :: (store (<8 x s32>))

...
---
name:            v2s64_umin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v2s64_umin
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), %vec(<2 x s64>), %vec1
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[SEXT_INREG]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
    ; CHECK-NEXT: %umin:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
    ; CHECK-NEXT: $q0 = COPY %umin(<2 x s64>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<2 x s64>) = G_IMPLICIT_DEF
    %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
    %umin:_(<2 x s64>) = G_UMIN %vec, %vec1
    $q0 = COPY %umin
    RET_ReallyLR implicit $q0

...
---
name:            v4s64_umin
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v4s64_umin
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
    ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
    ; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
    %vec:_(<4 x s64>) = G_IMPLICIT_DEF
    %vec1:_(<4 x s64>) = G_IMPLICIT_DEF
    %umin:_(<4 x s64>) = G_UMIN %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %umin(<4 x s64>), %1(p0) :: (store (<4 x s64>))

...
---
name:            v8s8_smax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: v8s8_smax
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<8 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %smax:_(<8 x s8>) = G_SMAX %vec, %vec1
    ; CHECK-NEXT: $x0 = COPY %smax(<8 x s8>)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %vec:_(<8 x s8>) = G_IMPLICIT_DEF
    %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
    %smax:_(<8 x s8>) = G_SMAX %vec, %vec1
    $x0 = COPY %smax
    RET_ReallyLR implicit $x0

...
---
name:            v16s8_smax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v16s8_smax
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<16 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %smax:_(<16 x s8>) = G_SMAX %vec, %vec1
    ; CHECK-NEXT: $q0 = COPY %smax(<16 x s8>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<16 x s8>) = G_IMPLICIT_DEF
    %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
    %smax:_(<16 x s8>) = G_SMAX %vec, %vec1
    $q0 = COPY %smax
    RET_ReallyLR implicit $q0

...
---
name:            v4s16_smax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: v4s16_smax
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %smax:_(<4 x s16>) = G_SMAX %vec, %vec1
    ; CHECK-NEXT: $x0 = COPY %smax(<4 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %vec:_(<4 x s16>) = G_IMPLICIT_DEF
    %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
    %smax:_(<4 x s16>) = G_SMAX %vec, %vec1
    $x0 = COPY %smax
    RET_ReallyLR implicit $x0

...
---
name:            v32s8_smax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v32s8_smax
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
    ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(<16 x s8>) = G_SMAX [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<16 x s8>) = G_SMAX [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[SMAX]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK-NEXT: G_STORE [[SMAX1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
    %vec:_(<32 x s8>) = G_IMPLICIT_DEF
    %vec1:_(<32 x s8>) = G_IMPLICIT_DEF
    %smax:_(<32 x s8>) = G_SMAX %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %smax(<32 x s8>), %1(p0) :: (store (<32 x s8>))

...
---
name:            v8s16_smax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v8s16_smax
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<8 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %smax:_(<8 x s16>) = G_SMAX %vec, %vec1
    ; CHECK-NEXT: $q0 = COPY %smax(<8 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<8 x s16>) = G_IMPLICIT_DEF
    %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
    %smax:_(<8 x s16>) = G_SMAX %vec, %vec1
    $q0 = COPY %smax
    RET_ReallyLR implicit $q0

...
---
name:            v16s16_smax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v16s16_smax
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
    ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(<8 x s16>) = G_SMAX [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<8 x s16>) = G_SMAX [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[SMAX]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK-NEXT: G_STORE [[SMAX1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
    %vec:_(<16 x s16>) = G_IMPLICIT_DEF
    %vec1:_(<16 x s16>) = G_IMPLICIT_DEF
    %smax:_(<16 x s16>) = G_SMAX %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %smax(<16 x s16>), %1(p0) :: (store (<16 x s16>))

...
---
name:            v2s32_smax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: v2s32_smax
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %smax:_(<2 x s32>) = G_SMAX %vec, %vec1
    ; CHECK-NEXT: $x0 = COPY %smax(<2 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %vec:_(<2 x s32>) = G_IMPLICIT_DEF
    %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
    %smax:_(<2 x s32>) = G_SMAX %vec, %vec1
    $x0 = COPY %smax
    RET_ReallyLR implicit $x0

...
---
name:            v4s32_smax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v4s32_smax
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<4 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %smax:_(<4 x s32>) = G_SMAX %vec, %vec1
    ; CHECK-NEXT: $q0 = COPY %smax(<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<4 x s32>) = G_IMPLICIT_DEF
    %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
    %smax:_(<4 x s32>) = G_SMAX %vec, %vec1
    $q0 = COPY %smax
    RET_ReallyLR implicit $q0

...
---
name:            v8s32_smax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v8s32_smax
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
    ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(<4 x s32>) = G_SMAX [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<4 x s32>) = G_SMAX [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[SMAX]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK-NEXT: G_STORE [[SMAX1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
    %vec:_(<8 x s32>) = G_IMPLICIT_DEF
    %vec1:_(<8 x s32>) = G_IMPLICIT_DEF
    %smax:_(<8 x s32>) = G_SMAX %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %smax(<8 x s32>), %1(p0) :: (store (<8 x s32>))

...
---
name:            v2s64_smax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v2s64_smax
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), %vec(<2 x s64>), %vec1
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[SEXT_INREG]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
    ; CHECK-NEXT: %smax:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
    ; CHECK-NEXT: $q0 = COPY %smax(<2 x s64>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<2 x s64>) = G_IMPLICIT_DEF
    %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
    %smax:_(<2 x s64>) = G_SMAX %vec, %vec1
    $q0 = COPY %smax
    RET_ReallyLR implicit $q0

...
---
name:            v4s64_smax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v4s64_smax
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
    ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
    ; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
    %vec:_(<4 x s64>) = G_IMPLICIT_DEF
    %vec1:_(<4 x s64>) = G_IMPLICIT_DEF
    %smax:_(<4 x s64>) = G_SMAX %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %smax(<4 x s64>), %1(p0) :: (store (<4 x s64>))

...
---
name:            v8s8_umax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: v8s8_umax
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<8 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %umax:_(<8 x s8>) = G_UMAX %vec, %vec1
    ; CHECK-NEXT: $x0 = COPY %umax(<8 x s8>)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %vec:_(<8 x s8>) = G_IMPLICIT_DEF
    %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
    %umax:_(<8 x s8>) = G_UMAX %vec, %vec1
    $x0 = COPY %umax
    RET_ReallyLR implicit $x0

...
---
name:            v16s8_umax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v16s8_umax
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<16 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %umax:_(<16 x s8>) = G_UMAX %vec, %vec1
    ; CHECK-NEXT: $q0 = COPY %umax(<16 x s8>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<16 x s8>) = G_IMPLICIT_DEF
    %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
    %umax:_(<16 x s8>) = G_UMAX %vec, %vec1
    $q0 = COPY %umax
    RET_ReallyLR implicit $q0

...
---
name:            v32s8_umax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v32s8_umax
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
    ; CHECK-NEXT: [[UMAX:%[0-9]+]]:_(<16 x s8>) = G_UMAX [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<16 x s8>) = G_UMAX [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[UMAX]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK-NEXT: G_STORE [[UMAX1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
    %vec:_(<32 x s8>) = G_IMPLICIT_DEF
    %vec1:_(<32 x s8>) = G_IMPLICIT_DEF
    %umax:_(<32 x s8>) = G_UMAX %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %umax(<32 x s8>), %1(p0) :: (store (<32 x s8>))

...
---
name:            v4s16_umax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: v4s16_umax
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %umax:_(<4 x s16>) = G_UMAX %vec, %vec1
    ; CHECK-NEXT: $x0 = COPY %umax(<4 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %vec:_(<4 x s16>) = G_IMPLICIT_DEF
    %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
    %umax:_(<4 x s16>) = G_UMAX %vec, %vec1
    $x0 = COPY %umax
    RET_ReallyLR implicit $x0

...
---
name:            v8s16_umax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v8s16_umax
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<8 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %umax:_(<8 x s16>) = G_UMAX %vec, %vec1
    ; CHECK-NEXT: $q0 = COPY %umax(<8 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<8 x s16>) = G_IMPLICIT_DEF
    %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
    %umax:_(<8 x s16>) = G_UMAX %vec, %vec1
    $q0 = COPY %umax
    RET_ReallyLR implicit $q0

...
---
name:            v16s16_umax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v16s16_umax
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
    ; CHECK-NEXT: [[UMAX:%[0-9]+]]:_(<8 x s16>) = G_UMAX [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<8 x s16>) = G_UMAX [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[UMAX]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK-NEXT: G_STORE [[UMAX1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
    %vec:_(<16 x s16>) = G_IMPLICIT_DEF
    %vec1:_(<16 x s16>) = G_IMPLICIT_DEF
    %umax:_(<16 x s16>) = G_UMAX %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %umax(<16 x s16>), %1(p0) :: (store (<16 x s16>))

...
---
name:            v2s32_umax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: v2s32_umax
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %umax:_(<2 x s32>) = G_UMAX %vec, %vec1
    ; CHECK-NEXT: $x0 = COPY %umax(<2 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %vec:_(<2 x s32>) = G_IMPLICIT_DEF
    %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
    %umax:_(<2 x s32>) = G_UMAX %vec, %vec1
    $x0 = COPY %umax
    RET_ReallyLR implicit $x0

...
---
name:            v4s32_umax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v4s32_umax
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<4 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %umax:_(<4 x s32>) = G_UMAX %vec, %vec1
    ; CHECK-NEXT: $q0 = COPY %umax(<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<4 x s32>) = G_IMPLICIT_DEF
    %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
    %umax:_(<4 x s32>) = G_UMAX %vec, %vec1
    $q0 = COPY %umax
    RET_ReallyLR implicit $q0

...
---
name:            v8s32_umax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v8s32_umax
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
    ; CHECK-NEXT: [[UMAX:%[0-9]+]]:_(<4 x s32>) = G_UMAX [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<4 x s32>) = G_UMAX [[BUILD_VECTOR]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[UMAX]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK-NEXT: G_STORE [[UMAX1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
    %vec:_(<8 x s32>) = G_IMPLICIT_DEF
    %vec1:_(<8 x s32>) = G_IMPLICIT_DEF
    %umax:_(<8 x s32>) = G_UMAX %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %umax(<8 x s32>), %1(p0) :: (store (<8 x s32>))

...
---
name:            v2s64_umax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v2s64_umax
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), %vec(<2 x s64>), %vec1
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[SEXT_INREG]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
    ; CHECK-NEXT: %umax:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
    ; CHECK-NEXT: $q0 = COPY %umax(<2 x s64>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %vec:_(<2 x s64>) = G_IMPLICIT_DEF
    %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
    %umax:_(<2 x s64>) = G_UMAX %vec, %vec1
    $q0 = COPY %umax
    RET_ReallyLR implicit $q0

...
---
name:            v4s64_umax
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0, $q0, $q1

    ; CHECK-LABEL: name: v4s64_umax
    ; CHECK: liveins: $x0, $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
    ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
    ; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
    %vec:_(<4 x s64>) = G_IMPLICIT_DEF
    %vec1:_(<4 x s64>) = G_IMPLICIT_DEF
    %umax:_(<4 x s64>) = G_UMAX %vec, %vec1
    %1:_(p0) = COPY $x0
    G_STORE %umax(<4 x s64>), %1(p0) :: (store (<4 x s64>))

...

